This invention relates to using the configuration bits of a programmable logic device as distributed random access memory (“RAM”). More particularly, this invention relates to reducing the costs of circuitry needed to implement distributed RAM in a programmable logic device.
A common type of programmable logic device (“PLD”) in use today uses static RAM bits to configure programmable logic components to implement a user logic design. It is known to provide circuitry in a PLD to allow a user to configure those configuration bits in otherwise unused portions of the PLD to function as RAM. For example, in some user designs, it may be more advantageous to use unused configuration bits as RAM rather than using a separate RAM device, because the amount of RAM needed is small, or because using on-chip RAM is faster. A RAM formed from such distributed configuration bits may be referred to as “distributed RAM.”
Contemporary PLDs are typically organized in a hierarchical structure, with basic logic units or elements arranged in groups which share local interconnection resources and other local resources. The configuration RAM bits typically are written to only during programming or configuration, and subsequently are not written to during normal device operation. Moreover, during configuration, it is typical for several bits to be written at once. Therefore, in previous attempts to use configuration memory as distributed RAM, decoders have been provided to allow the configuration bits to be written to individually. Those decoders have included a decoder for some group of configuration bits, plus up to three additional transistors per bit. In addition, separate signal paths for writing data into the distributed RAM have been added. As more transistors and signal paths are added to accommodate the distributed RAM, additional area is required and the cost increases, or alternatively the number of logic elements that can be made available for inclusion in distributed RAM must be limited, which limits user flexibility.
It would be desirable to be able to provide distributed RAM in a PLD at lower cost and with greater flexibility than has heretofore been possible.